1. Field of the Invention
The present invention relates to design methodologies for electrical circuits, and more particularly to a design methodology for application specific integrated circuits (ASICs), which allows a designer working on a module of an ASIC to more easily communicate and utilize design parameters from other designers working on different modules of the same ASIC.
2. Related Art
Circuit design is presently accomplished primarily through the use of computer aided design (CAD) tools, which take as input a circuit specification and automatically simulate and generate circuit descriptions suitable for implementation. One type of circuit commonly designed using CAD tools is an application specific integrated circuit (ASIC). ASICs are often very complex, and design of an ASIC is often accomplished by a group of designers working collectively on a single circuit or system. During the design process, ASICs are typically divided into a collection of modules, which are farmed out to different designers. This process gives rise to a number of communication problems, which can impede design progress, and can also lead to sub-optimal designs.
At the present time, modules are typically designed separately using the CAD tools, with little interaction between designers of different modules. CAD tools for circuits such as ASICs typically take as input a constraint file, specifying certain design parameters, such as worst case delay through a circuit, as well as a functional specification for the circuit. A CAD tool uses these inputs to achieve, if possible, a satisfactory design for a particular circuit module. Design parameters found in constraint files include, but are not limited to: (1) worst case delay for a signal through a module, (2) output load (capacitance) for a signal through a module, (3) size of a module, and (4) placement of the module within a circuit.
Constraint files are typically generated by hand from numbers that are agreed upon beforehand by the circuit designers. The designers will often assign a standard set of numbers for expected delays regarding a particular piece of circuitry in a constraint file. These estimated numbers are not exact, and the true numbers will often evolve over time, so that an original number will often overestimate or underestimate the ultimate value of an associated constraint. If this happens, additional design iterations may be required to achieve a satisfactory design.
Furthermore, as designs evolve during the design process, the input and output signal to a particular module can change. This presently necessitates manually editing the constraint file to reflect the new configuration of input and output signal. This re-editing process can be very time-consuming.
What is needed is a system to facilitate automatic communication of constraints between designers of different modules of a circuit, so that up-to-date constraint information is made available to designers of the different modules.
Additionally, what is needed is a process that automatically modifies a constraint file format when the underlying design changes, so that a constraint file does not need to be continually reformatted by hand when the design changes.